One example of the prior art is shown in a book entitled "Transmission Systems for Communications" published by members of the technical staff of Bell Telephone Laboratories in the revised fourth edition. On pages 742 to 744, a scrambler design is discussed and illustrated. On page 743, a scrambler is shown which checks for undesirable sequences, such as alternating 0's and 1's, and an all O state. On page 744, there is a statement that additional circuitry would be required if it became necessary to guard against an all logic 1 condition, in addition to the conditions guarded against in the circuitry shown. This approach requires a separate NAND gate, each having as many inputs as register bits, to detect each condition. These must be combined via additional circuitry to produce final control signal. Even then, a variant of the original troublesome bit pattern can still produce the undesired effect.
A self-synchronizing data scrambler suffers from th possibility of having an effective pattern match between the incoming data to be encoded and the current state of the scrambler register. The result of such a match causes an output which is no longer scrambled, but has a repetitive pattern. The probability of such a match is dependent upon the data source with the most likely patterns being an all 1's, an all 0's or an alternating 01 or 10 sequence. The general method in the prior art of preventing this type for scrambler failure, is to provide gates to monitor the register for the suspect patterns, and then either force a modification to the normal register input, or actually change some register bits directly, so as to perturb the pattern. The problem with the first mentioned approach is the possibility that the data pattern can still cause the problem to persist with yet a different pattern. The second prior art approach requires access to the individual register bits, and such access is often inconvenient when dealing with integrated circuits.
The method disclosed herein circumvents both of the above problems and provides pattern lockup protection independent of the data supplied, and further provides proper descrambling of this data.
This problem is circumvented in the present invention by monitoring certain (at least two) of the data bits in the storage register, and altering the logic value of the incoming data bit whenever the monitored bits have a prescribed logic value. Further, selected data bits are logically compared in a simultaneous comparison of a plurality of sets, including the presently supplied data bit, and whenever a given set of conditions is detected, the logic value of the data bit as supplied to the storage mean is altered to break the storage register pattern.
It is therefore an object of the present invention to provide an improved data scrambler, as well as an associated descrambler, to work with the data scrambler.